The Enhanced IDE/Fast-ATA FAQ
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The Enhanced IDE/Fast-ATA FAQ

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ATA: harddisks

10 ATA: harddisks

Contents of this section

This and the following sections of the FAQ are intended to provide additional background information for the curious. The answers here differ wildly in the depth in which they treat the material; pick and read at will. It's a FAQ, not a book.

10.1 How does ATA(-2) work?

To understand the basic concepts of advanced ATA drives, one first needs to understand the basics of drive technology. Basically, when the operating system needs data to be either read or written to secondary storage (the hard disk), the BIOS gets the command, and passes that command to the drive. For operating systems other than DOS, the BIOS is usually replaced by the operating system's own I/O subsystem; the principle remains the same.

How the command is passed, interpreted, and responded to, forms the basis for Advanced ATA. In a nutshell, there are seven registers that the BIOS writes to/reads from to create a command. An eighth register is used to read and write data. The signals that create these reads and writes are controlled by the BIOS, but their timing is determined by the interface hardware, and ATA specifications dictate how fast these signals can be asserted or deasserted. There are currently 4 modes of Programmed Input/Output (PIO) and 4 modes of Direct Memory Access (DMA). The numbers all of you have been reading about are only a small portion of these specifications, but they are the ones that marketing can tout best. These "transfer rates" are a result of the specification that controls how fast the I/O Read and Write cycle time of the data register can operate at.

10.2 What are PIO modes?

The PIO mode determines how fast data is transferred to and from the drive. In the slowest possible mode, PIO mode 0, the data cycle time can not exceed 600 nanoseconds. In a single cycle, 16 bits are transferred in or out of the drive. In a single sector, there are 256 words (16 bits = 1 word); 2048 sectors make up a megabyte. So, mathematically,
1 cycle 1 sector 1 megabyte 2000
-------- --------- ------------ = ------ = 3.3MB/s
600ns 256 words 2048 sectors 600ns
So, the theoretical transfer rate of PIO Mode 0 (600ns cycle time) is 3.3 megabytes per second.

Here are the rest of the PIO modes, with their respective transfer rates:
PIO mode Cycle timetransfer rate
(ns) (MB/s)
0 600 3.3 ATA
1 383 5.2 ATA
2 240 8.3 ATA
3 180 11.1 ATA-2, IORDY required
4 120 16.6 ATA-2, IORDY required
5 90 22.2 vaporware
The first three, PIO modes 0 to 2, are old modes also present in the old ATA standard. The others (PIO 3 and 4) are ATA-2 specific and use IORDY hardware flow control. This means the drive can use the IORDY line to slow down the interface when necessary. Interfaces without proper IORDY support may cause data corruption in the fast PIO modes; in that you're stuck with the slower modes, and typically half the bandwidth.

When interrogated with an Identify Drive command, a harddisk returns, among other things, information about the PIO and DMA modes it is capable of using.

10.3 What are DMA modes?

DMA or Direct Memory Access means that the data is transferred directly between drive and memory without using the CPU as an intermediary, in contrast to PIO. In true multitasking operating systems like OS/2 or Linux, DMA leaves the CPU free to do something useful during disk transfers. In a DOS/Windows environment the CPU will have to wait for the transfer to finish anyway, so in these cases DMA isn't terribly useful.

There are two distinct types of direct memory access: third-party DMA and first-party or busmastering DMA. Third-party DMA relies on the DMA controller on the system's mainboard to perform the complex task of arbitration, grabbing the system bus and transferring the data. In the case of first-party DMA, all this is done by logic on the interface card itself. Of course, this adds considerably to the complexity and the price of a busmastering interface.

Unfortunately, the DMA controller on ISA systems is ancient and slow, and out of the question for use with a modern harddisk. VLB cards cannot be used as DMA targets at all and can only do busmastering DMA. It is only on EISA- and PCI-based interfaces that non-busmastering DMA is viable: EISA type 'B' DMA will transfer 4MB/s, PCI type 'F' DMA between 6 and 8MB/s.

Today, all modern chipsets, including the ubiquitous Triton chipsets, incorporate a busmastering DMA capable ATA interface. Efforts to standardize the DMA hardware will ensure stable and reliable software support.

Anyway, the DMA modes supported are:
DMA Mode Cycle timetransfer rate
Single word(ns) (MB/s)
0 960 2.1 ATA
1 480 4.2 ATA
2 240 8.3 ATA
Multiword
0 480 4.2 ATA
1 150 13.3 ATA-2
2 120 16.6 ATA-2
DMA/16 120 16.6 Ultra-ATA
DMA/33 60 33.3 Ultra-ATA
The single word DMA modes are hardly useful and are obsoleted in ATA-3. Note that some older interfaces are able to use these DMA modes as a way to communicate with the drive, without actually doing direct memory access at all. In these cases, the DMA modes are just used as glorified PIO modes.

10.4 How are the ATA(-2,PI) I/O ports assigned?

The registers of the primary ATA channel occupy the following I/O addresses (in hexadecimal notation):
Register Read Function Write Function
01F0h Read Data Write Data
(16 Bits) (16 bits)
01F1h Error register Set Features Data
01F2h Status of sector Write sector count
count for command setup
01F3h Location of starting Write sector start
sector for command setup
01F4h Location of Cyl-low Write cyl-low location
for command setup
01F5h Location of Cyl-high Write cyl-high location
for command setup
01F6h Head/device selection Write device selection
and head selection for
command setup
01F7h Device Status Device command
03F6h Alternate Status Device Control
03F7h Drive Address
Note that the floppy disk controller's disk change flag shares 03F7h which makes life difficult for designers that want to implement disk and floppy controllers separately. From this point of view it may come as no surprise that some of the problems in the CMD640x and RZ1000 'EIDE' interface chips touched upon elsewhere in this FAQ are floppy related.

There is no reason why there can't be a large number of interfaces like this one. There is a de facto standard for four of these ports:
Interface number CS0-decode CS1-decode IRQ number
1 01F0h-01F7h03F6h-03F7h 14
2 0170h-0177h0376h-0377h 15 or 10
3 01E8h-01EFh03EEh-03EFh 12 or 11
4 0168h-016Fh036Eh-036Fh 10 or 9
Only the first two enjoy really widespread support; for the secondary port, IRQ15 is the most commonly used interrupt by far. Potential BIOS support for arbitrary extra ports is found only in the Phoenix specification.

10.5 What does an ATA-2 interface do?

Interfaces have come a long way since the ordinary ISA IDE consisting of little more than a simple buffer. ATA-2 boards have to support at least PIO modes 0 and 3, usually support many more modes, and will have to ensure that the correct timing is used at the ATA interface for each of these modes. Since the timing specifications are quite complicated, a great deal of flexibility is necessary to implement the ATA-2 standard correctly.

                             |<------------ t0 ------------------------>|
                       __________________________________________       |
Address Valid *1 _____/                                          \________
                      |<-t1->|<----------- t2 ----------->|<-t9->|      |
                      |      |____________________________|<---t2i----->|_
DIOR-/DIOW-      ____________/                            \_____________/
                      |      |                            |      |
                      |      |                    ________|__  ->|   |<-t8
Write Data    *2 --------------------------------<___________>------------
                      |      |                   |<--t3-->|  |       |
                      |      |                          ->|t4|<-     |
                      |      |                     _______|___ ____  |
Read Data     *2 ---------------------------------<___________X____>------
                    ->|t7|<- |                    |     ->|t6 |<-  | |
                      |  | ->| tA |<-             |<-t5-->|<-t6Z-->|
                      |  |___________________________________________|
IOCS16-          ________/        |               |                  \____
                                  |             ->|tRd|<-            |
                 _________________|___________________|___________________
IORDY            XXXXXXXXXXXXXXXXX____________________/
                                  |<-------tB-------->|
  *1 Device Address consists of signals CS0-, CS1- and DA2-0
  *2 Data consists of DD0-15 (16-bit) or DD0-7 (8-bit)

The above figure defines the relationships between the interface signals for both 8-bit and 16-bit PIO data transfers.

In this diagram, t0 denotes the read/write cycle time, the most significant determining parameter for PIO mode throughput. As you can see, there is a lot more to the various PIO and DMA modes than this read/write cycle time only. To design a low-cost interface that fully adheres to the ATA-2 specification is quite a challenge. The common approach is to make the timing completely software programmable; unfortunately, the way ATA cards are programmed has not been standardized and differs radically between cards. The consequence is that you will typically need interface-specific drivers for each and every operating system used in order to profit from the fast transfer modes.

10.6 What is Block mode?

Multiple Read/Write commands (reduces Interrupts to host processor).

Besides the obvious transfer increase, Fast-ATA and many other drives allow for Read/Write Multiple commands, which increase the number of sectors passed without intervening interrupts. This lessens the host's overhead, as every interrupt causes the CPU to do a context switch, check the device and set up the data transfer (or perform the transfer itself in the case of PIO).

The Read Multiple Command (0C4h) and the Write Multiple Command (0C5h) are drive-level commands that can transfer multiple sectors of data without asserting the IRQ line of the drive, signaling the processor that a drive operation is pending.

The IRQ line is asserted when:

  • A read command has been issued, and the requested data is in the drive's buffer, ready to be taken by the host.
  • A write command has been issued, and the data has transferred to the drive's buffer. If write caching is disabled, the IRQ won't be asserted until the data has been completely written to the media.

During normal reads and writes, the interrupt can constantly bother the CPU, and depending on the processor and the task at hand (multi-tasking OS, Unix, etc), there can be long delays in having the CPU service the drive. The advent of Read/Write Multiple allows many sectors (from 2 up to as many as 128) to be transferred in one go, completing the task in as much as 30% faster times.

On single-tasking operating systems like DOS, any improvement over a few percent usually indicates bad buffer cache management on the part of the drive.

Warning: some old drives have a buggy block mode implementation and may corrupt data.

A final remark: the block size that is optimal for drive throughput doesn't have to be the best for system performance! For example, the DOS FAT filesystem tends to favor a block size equal to the cluster size. Do not trust low level benchmarks when tweaking the block size, but use an application level benchmark suite instead.

10.7 What is LBA?

LBA is a means of linearly addressing sectors addresses, beginning at sector 1 of head 0, cylinder 0 as LBA 0, and proceeding on to the last physical sector on the drive, which, for instance, on a standard 540 Meg drive would be LBA 1,065,456. This is new in ATA-2, but has always been the one and only addressing mode in SCSI. Note that LBA does not allow you to address more sectors than CHS style addressing would.

LBA reduces CPU overhead in OSs that use LBA internally, but on the other hand takes a little more time when ordinary CHS based BIOS calls are used (eg. DOS). Beware that depending on the way LBA is implemented in the harddisk firmware, the overhead on the part of the drive may increase.

10.8 How does security work?

Security mode implements a simple password protection scheme. Security can affect just write operations, or both reads and writes. Non-data operations (such as Identify Device) can always be executed regardless of the security status.

There are two security levels: High and Maximum. If the user password is lost and High level security is set, the drive can still be unlocked with the Master password. At Maximum level, there is no way to unlock the drive without erasing all user data.

After a number of incorrect passwords the drive will reject further passwords until a powerdown or hard reset. This makes guessing the password by brute force very difficult.

10.9 What is S.M.A.R.T.?

S.M.A.R.T. or Self Monitoring Analysis and Reporting Technology allows the drive to report about certain types of degradation or impending failure. This allows the operating system to take the necessary precautions and warn the user. The OEM release 2 of Win95 and the next OS/2 version (Merlin) will be SMART aware.

The utility of this feature will initially be quite limited, though, because many failure modes (including the infamous Monday morning failure) can't be sensed in advance.

At present only few utilities exist to examine the S.M.A.R.T. status of a drive. These include Micro House EZ-S.M.A.R.T. and Symantec S.M.A.R.T. Doctor.

10.10 What is PRML?

The Partial Response Maximum Likelihood or PRML read channel is quickly replacing the ordinary peak detection channel as a mass market technology. Briefly, where a peak detection channel uses a comparatively simple analogue technique to extract the digital data from the signal picked up by the read head, a PRML channel digitizes the signal and employs digital processing techniques to reconstruct the data. Thanks to these DSP techniques a PRML channel can still work reliably on very closely packed data where the distinction between individual bits tends to blur. The end result is a faster, higher capacity drive.

For a more thorough discussion of this topic, take a look at Quantum's excellent white papers .

10.11 What are MR heads?

Magnetoresistive or MR drive heads are quickly replacing the old inductive heads in all sections of the harddrive market. For more information, see for example http://www.seagate.com/new/sep96/mr_techp.shtml .

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